1. Field of the Invention
The present invention relates to an integrated circuit provided with electrostatic discharge (ESD) protection circuitry, and to a method of providing ESD protection within such an integrated circuit.
2. Description of the Prior Art
Typically an integrated circuit will comprise the functional circuitry needed to perform the processing functions of the integrated circuit, along with interface circuitry (often referred to as input/output (I/O) circuitry) for providing an interface between the functional circuitry and components external to the integrated circuit. Often the interface circuitry takes the form of an I/O ring surrounding the functional circuitry and incorporating all of the required I/O cells to facilitate the input/output requirements of the integrated circuit.
An integrated circuit can be subjected to various ESD sources, and it is necessary to protect the functional circuitry from those ESD sources. Typically, this is achieved by incorporating ESD protection circuits within the relevant I/O cells of the I/O ring.
As integrated circuits increase in size and complexity, and incorporate functionalities such as multiple power domains, this can give rise to significant challenges when designing the associated I/O ring. In particular, as the I/O count increases, then this gives rise to significant space constraints within the I/O ring, leading to the requirement for more and more space efficient designs for the various I/O cells, including the I/O cells incorporating ESD protection circuits. With the additional complication of multiple power domains, it is also necessary to provide suitable ESD protection for all of the various power domains.
Advancements in integrated circuit implementation techniques also provide further challenges for ESD protection mechanisms. For example, flip-chip assembly techniques for integrated circuits provide an array of bump connection points allowing external connections to be established at various places within the chip, and not restricted to the I/O ring. Whilst such a flip-chip assembly can provide improved flexibility, for example in the establishment of multiple power domains by allowing power connections to be made to appropriate bump connection points, it complicates the issue of providing suitable ESD protection for the various power domains, due to the routing required to the ESD protection circuits within the I/O ring.
The article “Comprehensive ESD Protection for Flip-Chip Products in a Dual Gate Oxide 65 nm CMOS Technology” by J Miller et al, EOS/ESD Symposium 06/186, 4A, 4-1 to 4-10, describes a modular ESD rail clamp network configuration for use in flip-chip products. In accordance with the described technique, all required ESD elements for an output VDD (OVDD) segment are wholly contained within the I/O cells for that segment, without the need for power/ground or spacer cells. Whilst such an approach can enable space savings to be achieved within the I/O ring due to the more efficient design, a significant issue that still arises is how to efficiently couple groups of functional components within the functional circuitry (for example a group of functional components associated with a particular power domain) with the ESD protection elements provided within the I/O ring. In particular, if the group of functional components lies relatively distant from the I/O ring (for example towards a central region of the integrated circuit), then it can be very difficult, and infeasible in certain situations, to find appropriate routing paths between the components and the associated ESD protection elements within the I/O ring. Even when routing can be found, if that routing is relatively long, there will be additional resistance in the path between the functional components and the ESD protection circuitry, which can lead to an increase in the size of the ESD clamp required, thereby increasing the space requirements for the ESD protection circuitry within the I/O ring.
The article “ESD Protection Design Challenges for a High Pin-Count Alpha Microprocessor in a 0.13 μm CMOS SOI Technology” by P Juliano et al, EOS/ESD Symposium Proceedings 2003, describes an integrated circuit arrangement where the floor plan is modified so as to incorporate a number of separate I/O blocks within the area of the integrated circuit, rather than using a traditional I/O ring. Whilst the use of such distributed I/O blocks can alleviate some of the earlier-mentioned routing problems by allowing the ESD protection circuitry within the relevant I/O cells to be located physically closer to the relevant functional components, it significantly reduces flexibility when compared with an I/O ring, due to the placement of the various I/O blocks having to be fixed at the floor planning stage. The use of such I/O cells without an I/O ring also impacts flexibility, since there is then a requirement to use a flip-chip implementation, preventing any wirebond packaging possibility. In addition, when considering the various layers that are used to implement an integrated circuit on a substrate, I/O cells are typically very “high”, occupying virtually all of the layers constituting the integrated circuit. For example, considering the earlier-described flip-chip implementation, the I/O cells will typically extend through all of the layers from the silicon substrate up to the redistribution (RDL) layer. Hence, wherever the I/O blocks are placed, they provide an effective bather between functional components residing on one side and functional components residing on the other, this hence placing very significant constraints on the integrated circuit design.
Accordingly, it would be desirable to provide an improved ESD protection arrangement for an integrated circuit.